1. Field of the Invention
The present invention is in the field of circuit elements containing integrated MOS transistors and comprising a semiconductor substrate composed of silicon having an overlying gate oxide. The gate metallization applied over the gate oxide is composed in part of a metal or metal silicide of tantalum or niobium.
2. Description of the Prior Art
Doped, polycrystalline silicon is utilized as a standard material for gate contacting (gate metallization) in LSI (large scale integrated) MOS (metal oxide semiconductor) semiconductor technology. The principal reason for this is that with a thin gate oxide approximately 20 nm usually composed of SiO.sub.2, the polysilicon has extremely stable and highly reproducible boundary surface properties. Among these are low mechanical stresses, low leakage currents, high punch-through voltage and defined work function. These properties, in turn, directly define the electrical behavior of the MOS transistor. The conductivity of the polysilicon layer is expressed by means of its surface resistance which represents the resistivity divided by the thickness. Since a specific electrical resistance at a minimum of 800 micro-ohms can be assumed for highly doped polysilicon, a surface resistance of 16 ohms is obtained for a layer that is 500 nm thick.
In VLSI (very large scale integrated) MOS technology, the size of the electrically active regions in the semiconductor substrate is reduced to dimensions of 1 micron or below so that, for example, the diameter of contact holes or the width of the interconnects is also in this size range. This, in turn, creates the possibility of increasing the number of sub-units, such as memory units, per component.
The result of this development is that the bulk resistance rises greatly with reduced cross section and increased length of the connecting lines of doped polysilicon. An increase in the RC time constants of the component is thereby produced, resulting in a decisive reduction of the switching speeds. For DRAM (dynamic random access memory) memory components having more than 256 kilobit memory units, this can mean an increase in the memory access time in comparison to components, (for example 64 kilobit DRAMs), which do not have such large scale integration.
In order to avoid such effects, for example, in dynamic memory components having more than 1 megabit memory capacity and in order to be able to meet the demands regarding packing density, a surface resistance of about 0.3 to 0.6 ohms with a maximum layer thickness of 500 nm must be met for the metallization layer in the gate level. Such low values of resistance can no longer be achieved even with extremely highly doped polysilicon. A new material is thus required which has a high electrical conductivity and which also does not deteriorate the property of the extremely thin gate oxide of SiO.sub.2 even at high temperatures, for example, at 900.degree. C. which are necessary in the manufacturing process. A further, very important requirement is that the material can be easily integrated into already existing manufacturing processes for semiconductor components without great expenditure.
The electrical resistance of the metallization layer in the gate level can be reduced by partially replacing the polycrystalline silicon by a disilicide layer of molybdenum, tungsten, tantalum or titanium as described, for example, in an article by S. P. Murarka in J.Vac.Sci.Technol. 17 (1980), pages 775 to 792. The materials combination is based on the fact that the disilicides of the metals no longer react with silicon even at temperatures of 1000.degree. C. In an atmosphere containing oxygen, this combination of materials forms an SiO.sub.2 passivation layer on the disilicide. Since a thin polysilicon layer (about 200 nm) remains between the gate oxide and the disilicide, the favorable electrical properties and the long-term stability of the polysilicon-SiO.sub.2 boundary layer are not adversely affected. Very high compatibility with the existing polysilicon gate process is achieved with this double layer of 200 nm polysilicon and 300 nm disilicide but the surface resistances achieved are at best 0.6 to 0.8 ohms even with the lowest impedance disilicide (the resistivity of titanium silicide is 25 micro-ohm cm).
Where a pure silicide metallization is used in which the disilicide is in direct contact with the gate oxide, then, due to the higher work function of the silicides in comparison to polysilicon, the resulting circuit would have additional advantages. Titanium silicide, however, would be the only disilicide with which the required surface resistance would be obtained at a thickness of 500 nm. As reported by S. P. Murarka in the book "Silicides for VLSI Applications", Academic Press, 1983, page 30, the specific values of resistance of co-sputtered tantalum disilicide is at about 50 micro-ohm cm, and that of co-sputtered tungsten disilicide being about 70 micro-ohm cm. The high reactivity of the titanium silicide at about 900.degree. C., which is a common processing temperature, leads to a reaction with the SiO.sub.2 whereby TiO.sub.2 remains as the final product, and the gate oxide is thereby destroyed.
U.S. Pat. No. 4,337,476 discloses that a stable gate metallization is possible using an excess of silicon in the titanium disilicide or the tantalum disilicide. However, it is also known from an article by P. S. Murarka and D. B. Fraser in J. Appl. Phys., 51 (1980) pages 1593 to 1598, that these materials have an elevated specific electrical resistance in comparison to the disilicide of stoichiometric proportions.
The use of the pure metals molybdenum and tungsten provides difficulties insofar as these two metals do not form a passivation layer and volatile oxides can even arise in an atmosphere which contains oxygen. Additional manufacturing steps such, for example, as heating in a humid hydrogen atmosphere or covering the metal with oxides must therefore be used. An additional difficulty in the combination of molybdenum or tungsten with SiO.sub.2, due to the low chemical affinity between the materials, is that the adhesion of these materials to the gate oxide is deficient. A solution to this might be achieved in using a thin (for example, 50 nm) intermediate layer of a silicon-rich tungsten disilicide or molybdenum disilicide or in utilizing a molybdenum-tungsten alloy with about 8 mol % tantalum as a layer between the SiO.sub.2 gate and the pure molybdenum. For MOS production lines in which the combination of tantalum disilicide and polysilicon as gate metallization or tantalum disilicide containing 35 mol % tantalum as a diffusion barrier between silicon and aluminum have heretofore been employed, but the introduction of an additional material such as molybdenum or tungsten for a low impedance gate metallization represents a serious modification and a relatively great expenditure for apparatus. A corresponding gate material based upon tantalum which might be of great economic interest in these production lines is still unavailable.